In February 2023, the General Research Institute of Industrial Technology (AIST) in Japan, in conjunction with Tokyo Metropolitan University, announced that the layered material antimony telluride (Sb2Te3) has been successfully formed on molybdenum disulfide (MoS2) and produced N-type MoS2 transistors with sufficient heat resistance to withstand the semiconductor manufacturing process. A material called transition metal disulfides (TMDC), which has a two-dimensional crystal structure, is of interest as a semiconductor material for the channel of the next generation transistor because of its ability to maintain high conductivity even in atomic layer regions of 1 nanometers or less. However, the high contact resistance between the common metal electrode and the MoS2 interface prevents the transistor from improving performance. AIST is participating in the Japanese Science and Technology Agency's Strategic Basic Research Promotion Program (CREST) "Demonstration of Atomic Layer heterogeneous devices and development of atomic layer deposition processes for 3D integrated LSI (FY2017-2021) : Metropolitan I has been working on high-performance TMDC transistors in a joint project with the university. This time, the team built transistors using MoS2 and focused on Sb2Te3 as its contact material. Sb2Te3 has many layers of atoms held together by weak bonds called van der Waals forces. It also exhibits properties similar to semi-metals (band gap 0.2 to 0.3 eV) and has a high melting point of about 620°C. These characteristics suggest that a van der Waals interface may be formed between Sb2Te3 and MoS2 to inhibit Fermi level pinning (FLP). Therefore, it was determined that high heat resistance and low contact resistance could be achieved simultaneously by using Sb2Te3. Thus, this time, a Sb2Te3 film is formed on a monolayer MoS2 using sputtering. The formation of a van der Waals interface at the Sb2Te3/MoS2 interface was then confirmed by transmission electron microscopy (TEM). The heat resistance of Sb2Te3/MoS2 laminates was also investigated. Raman spectrum analysis confirmed that the single layer structure of MoS2 remained unchanged before and after heat treatment. It was also confirmed that the Sb2Te3/MoS2 lamination structure maintained good crystallinity and van der Waals interfaces even after heat treatment at 450°C. The team also investigated the effect of the formation of the Sb2Te3/MoS2 van der Waals interface on the characteristics of the transistor. It is found that the driving current of the transistor with Sb2Te3 electrode is 4 to 30 times higher than that when Sb, Ni, W, etc., are used as contact materials. In fact, when measuring the contact resistance of a MoS2 transistor, the contact resistance value of a transistor using the Sb2Te3 electrode is about an order of magnitude lower than that of a transistor using the Sb electrode. In the future, our research group will focus on the development of low contact resistance technology for P-type TMDC transistors, aiming to manufacture CMOS through N-type and P-type TMDC transistors in series. Taiwan Semiconductor engineers, in collaboration with two Taiwanese universities, will report the world's first nanosheet gate ring transistor made from two-dimensional semiconductor materials at this year's International Conference on Electronic Devices (IEDM). Silicon nanosheet transistors or aka nanoribbons offer improved electrostatic control and relatively high drive currents and are implemented in 3nm manufacturing processes. According to the highlights of the upcoming IEDM initiative, TSMC has demonstrated the possibility of using a single layer of transition metal disulfide as a semiconductor channel in nanosheet transistors. In this case, it's molybdenum disulfide. Such two-dimensional materials can have enhanced electron mobility compared to silicon and spin-orbit coupling, resulting in spintronic computing possibilities. A transistor with a gate width of 40nm produces a drive current of 410 microamperes per micron at 1V Vds. Stacking devices is expected to increase the drive current. The TSMC led team will report on the integration process for making such transistors, but optimizing the performance remains to be completed. TSMC Paper #34.5 First Presentation of GAA Monolayer MoS2 Nanosheet nFET... Was one of the highlights of the 68th annual IEDM. In paper #7.4, in a near-ideal subthreshold swing in a top-gate nFET of a single-layer MoS2 with an EOT of 1 nm, the TSMC led team describes the integration of hafnium-based dielectrics with MoS2 to build a top-gate nFET to create stackable systems. The subthreshold voltage swing is less than 70mV/dec. This indicates that the leakage current is lower when the transistor is turned off. Major breakthrough in the manufacturing process below 1 nm! Shortly after IBM announced the development of 2nm chips, Taiwan Semiconductor Manufacturing Co., LTD. (TSMC) has launched another challenge. TSMC has made major breakthroughs in manufacturing processes below 1nm, constantly challenging the physical limits. Recently, the National Taiwan University, Taiwan Semiconductor Manufacturing Company and the Massachusetts Institute of Technology have found that the two-dimensional material combined with "semi-metallic bismuth (Bi)" can achieve very low resistance, close to the quantum limit. The research results, which have been published in the international journal Nature, were jointly carried out by Wu Zhiyi, professor of the Department of Electrical Machinery and Institute of Photonics at National Taiwan University, and the research team of Taiwan Integrated Circuit and MIT, and could help achieve the challenge of semiconductor manufacturing processes below 1nm. At present, the mainstream semiconductor process progress to 5nm and 3nm node. The number of transistors that can be accommodated per unit area of a wafer has approached the physical limit of the mainstream semiconductor material "silicon", and the wafer efficiency can no longer be significantly improved year by year. In recent years, the scientific community is actively looking for 2D materials that can replace silicon, challenging the process below 1nm, but unable to solve the problems of high resistance and low current of 2D materials. Since 2019, Taiwan National University, Taiwan Semiconductor Manufacturing and MIT have carried out 1 1/2 years of cross-border cooperation and finally found this key. The breakthrough came after the MIT team discovered that a "two-dimensional material" electrode paired with a "semi-metallic bismuth (Bi)" could drastically reduce resistance and increase transmission current. The Technical research department of Taiwan Semiconductor Manufacturing Company optimized the bismuth (Bi) deposition process. Finally, the team at Taiwan Semiconductor Company successfully reduced the component channel to nanometer size using the helium ion Beam microshadow System. By using bismuth (Bi) as the key structure of the contact electrode, the performance of the two-dimensional material transistor is not only comparable to that of the silicon based semiconductor, but also has the potential to be compatible with the current mainstream silicon based process technology, helping to break the limits of Moore's Law in the future, said Professor Wu Zhiyi. The research results can provide the next generation of wafers with excellent conditions such as power saving and high speed, and it is expected to be applied in artificial intelligence, electric vehicles, disease prediction and other emerging technologies in the future. TSMC goes 2nm! For decades, a golden rule has been behind the semiconductor industry's progress: Moore's Law. Moore's Law states that every 18 to 24 months, the number of components that can fit on an integrated circuit doubles, and so does the chip's performance. However, in Moore's Law has slowed down or even failed today, the world's major semiconductor companies are still desperately "fighting", hoping to take the lead in the manufacturing process layout commanding heights. TSMC is a clean SLATE when it comes to advanced manufacturing. In the 3nm field, Taiwan Semiconductor Manufacturing Co., LTD. In 2020, 5nm was mass-produced. The 2nm is expected to launch between 2023 and 2024. As previously reported, TSMC's entire advanced manufacturing process has been laid out in recent years: remember, TSMC, Intel, and Samsung are known as the "Big Three" in semiconductor manufacturing. The Big Three are chasing each other as the chip process shrinks. Now along comes IBM, which announced last week that it has developed the world's first 2nm chip, which can fit up to 50 billion transistors on a chip the size of a fingernail, faster and more efficient. For the more advanced 2nm process, TSMC announced its development as early as 2019. Last year, shortly after 5nm went into mass production, TSMC announced a breakthrough in the 2nm process -- gate-all-around (GAA) technology. Different from 3nm and 5nm, FinFET architecture is adopted. The FinFET itself has been reduced to the limit of its size, and the fin-fin distance, short-channel effect, leakage and material limits also make the fabrication of transistors precarious and even the physical structure impossible. GAA is an evolution of FinFET technology. The channel is composed of nanowire and surrounded by grids on all sides, thus enhancing the grid's control over the channel and effectively reducing leakage. TSMC introduced full-loop gate FET GAA into 2nm development, while its rival Samsung announced to switch from FinFET to GAA two years ago when it revealed the 3nm technology process, and made a "big talk" that it would overtake TSMC and become the global chip foundry leader by 2030. This is a clarion call for the two companies to compete in the 2-3nm process market. In order to beat TSMC to 3nm, Samsung's chip manufacturing process went straight from 5nm to 3nm and skipped 4nm. While TSMC and Samsung are battling it out in the 2nm-3nm market, Intel doesn't care, sticking to the 14nm and 10nm processes. Taiwan Semiconductor, Samsung's pursuit of the most advanced processes, is trying to compete in the world's most advanced processes. At the same time, out of interest, the world's largest contract wafer manufacturer, Taiwan Semiconductor Industry is also actively seeking to establish a factory in the United States, one of the efforts is to join the newly formed "American semiconductor Alliance". On Tuesday, the Semiconductors in American Coalition (SIAC), a lobby group led by American technology companies, was launched. SIAC's members currently include Apple, Google, Microsoft and Intel, as well as leading American tech firms such as Samsung and Hynix, as well as the lithography giant ASML and the island's leading wafer makers Taiwan Semiconductor Manufacturing and Mediatek. Taiwan Semiconductor did not respond specifically to the news of joining SIAC. In a partial screenshot of the "Members" page of SAIC's official website, it can be seen that TSMC lists the limitations of any of these members as impeding our development. Experts say it could make it harder for China to achieve its goal of becoming self-sufficient in semiconductors without relying on U.S. technology. SIAC's immediate task is to urge the US government to provide "subsidies". A bipartisan group of US senators on Friday unveiled a "$52bn" proposal to dramatically boost semiconductor chip production and research in the US over five years. Us Senator Mark Kelly and others have been discussing a compromise to "address rising semiconductor production in China and the impact of the chip shortage on car manufacturing and other US industries". The proposal is expected to be included in a bill the Senate will take up next week to fund basic and advanced technology research in the United States. In addition to the $52 billion proposal, the Senate Commerce, Science and Transportation Committee voted 24:4 in favor of the "Endless Frontiers" bill on May 12, authorizing "$110 billion" over five years for science and technology research, The Hill reported. The Endless Frontier bill would authorize $100 billion of that investment over five years in basic and advanced technology research, commercialization, education, and training programs, including artificial intelligence, semiconductors, quantum computing, advanced communications, biotechnology, and advanced energy. In addition, the bill includes "$10 billion" more to set up at least 10 regional technology centers and create a supply-chain crisis plan to address issues such as the "semiconductor chip gap" hurting auto production. Alex Capri, a researcher at the Hinrich Foundation and a lecturer at the National University of Singapore, said that because the US is aggressively transferring the semiconductor value chain and technology back to the US and setting up a protective net, "mainland China's efforts to upgrade the chip industry will be more challenging". Mr Capri believes that a significant increase in Taiwan Semiconductor's investment in the US and its involvement in building leading 5nm or even 3nm chip manufacturing plants in the US could put pressure on China, as it is clear that Taiwan Semiconductor will not build such plants in China. TSMC confirmed last month that it had invested $2.9bn to expand the Nanjing plant, but the technology is a 28nm process, two to three generations behind the technology it uses at its Arizona fab. TSMC, like other companies that joined SIAC, is motivated by self-interest and has the opportunity to carve up the $50 billion in U.S. government funds, said Richard Landall, head of Intralink's electronics and embedded software division. At the same time, he said, China has no such grouping of companies from around the world, and alliances help the United States and its Allies "stay ahead of China in the long run."